HD6433044 Datasheet, PDF (310/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

10.1.2 Block Diagrams
ITU Block Diagram (Overall): Figure 10-1 is a block diagram of the ITU.
TCLKA to TCLKD
ø, ø/2, ø/4, ø/8
TOCXA₄, TOCXB₄
TIOCA₀ to TIOCA₄
TIOCB₀ to TIOCB₄
Clock selector
Control logic
IMIA0 to IMIA4
IMIB0 to IMIB4
OVI0 to OVI4
TOER
TOCR
TSTR
TSNC
TMDR
TFCR
Module data bus
Legend
TOER: Timer output master enable register (8 bits)
TOCR: Timer output control register (8 bits)
TSTR: Timer start register (8 bits)
TSNC: Timer synchro register (8 bits)
TMDR: Timer mode register (8 bits)
Figure 10-1 ITU Block Diagram (Overall)
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