HD6433044 Datasheet, PDF (651/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Table 20-1 Power-Down State and Module Standby Function
State
Mode
Entering
Conditions
Clock CPU
CPU
Refresh
Registers DMAC Controller ITU
SCI0 SCI1 A/D
Other
ø clock
Modules RAM output
I/O
Ports
Exiting
Conditions
Sleep
mode
SLEEP instruc- Active Halted Held
tion executed
while SSBY = 0
in SYSCR
Active Active Active Active Active Active Active Held ø output Held
• Interrupt
• RES
• STBY
Software SLEEP instruc- Halted Halted Held
standby tion executed
mode while SSBY = 1
in SYSCR
Halted Halted Halted Halted Halted Halted Halted Held High
Held
and
and
and
and
and
and
and
output
reset
held^*1
reset reset
reset reset reset
• NMI
• IRQ₀ to IRQ₂
• RES
• STBY
Hardware Low input at
standby STBY pin
mode
Halted Halted Undeter-
mined
Halted
and
reset
Halted
and
reset
Halted
and
reset
Halted
and
reset
Halted
and
reset
Halted
and
reset
Halted
and
reset
Held^*3 High
High
• STBY
impedance impedance • RES
Module Corresponding Active Active —
standby bit set to 1 in
MSTCR
Halted^*2 Halted^*2 Halted^*2 Halted^*2 Halted^*2 Halted^*2 Active —
and
and
and
and
and
and
reset
held^*1
reset reset
reset reset
High
impedance^*2
• STBY
• RES
• Clear MSTCR
bit to 0^*4
Notes: 1. RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their previous states.
2. State in which the corresponding MSTCR bit was set to 1. For details see section 20.2.2, Module Standby Control Register (MSTCR).
3. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode.
4. When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first clear the MSTCR bit to 0,
then set up the module registers again.
Legend
SYSCR: System control register
SSBY: Software standby bit
MSTCR: Module standby control register