HD6433044 Datasheet, PDF (218/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Bits 2 to 0—Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the
data transfer activation source. The selectable activation sources differ between normal mode and
block transfer mode.
Normal mode
Bit 2 Bit 1 Bit 0
DTS2B DTS1B DTS0B Description
0
0
0
Auto-request (burst mode)
1
Cannot be used
1
0
Auto-request (cycle-steal mode)
1
Cannot be used
1
0
0
Cannot be used
1
Cannot be used
1
0
Falling edge of DREQ
1
Low level input at DREQ
(Initial value)
Block transfer mode
Bit 2 Bit 1 Bit 0
DTS2B DTS1B DTS0B Description
0
0
0
Compare match/input capture A interrupt from ITU channel 0 (Initial value)
1
Compare match/input capture A interrupt from ITU channel 1
1
0
Compare match/input capture A interrupt from ITU channel 2
1
Compare match/input capture A interrupt from ITU channel 3
1
0
0
Cannot be used
1
Cannot be used
1
0
Falling edge of DREQ
1
Cannot be used
The same internal interrupt can be selected to activate two or more channels. The channels are
activated in a priority order, highest priority first. For the priority order, see section 8.4.9, DMAC
Multiple-Channel Operation.
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