HD6433044 Datasheet, PDF (291/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

9.11.2 Register Descriptions
Table 9-18 summarizes the registers of port A.
Table 9-18 Port A Registers
Address* Name
Abbre-
viation R/W
H'FFD1 Port A data direction PADDR W
register
H'FFD3 Port A data register PADR
R/W
Note: * Lower 16 bits of the address.
Initial Value
Modes 1, 2, 5 and 7 Modes 3, 4, and 6
H'00
H'80
H'00
H'00
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
Bit
7
6
5
4
3
2
1
0
PA₇ DDR PA₆ DDR PA₅ DDR PA₄ DDR PA₃ DDR PA₂ DDR PA₁ DDR PA₀ DDR
Modes
3, 4,
Initial value
1
0
0
0
0
0
0
0
and 6 Read/Write —
W
W
W
W
W
W
W
Modes
1, 2, 5,
Initial value
0
and 7 Read/Write W
0
0
W
W
0
0
0
W
W
W
0
0
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input
pin if this bit is cleared to 0. In modes 3, 4, and 6, PA₇DDR is fixed at 1 and PA₇ functions as an
address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, and 7.
It is initialized to H'80 by a reset and in hardware standby mode in modes 3, 4, and 6. In software
standby mode it retains its previous setting. If a PADDR bit is set to 1, the corresponding pin
maintains its output state in software standby mode.
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