HD6433044 Datasheet, PDF (339/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF IMFB IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
— R/(W)* R/(W)* R/(W)*
Reserved bits
Overflow flag
Status flag indicating
overflow or underflow
Input capture/compare match flag B
Status flag indicating GRB compare
match or input capture
Input capture/compare match flag A
Status flag indicating GRA compare
match or input capture
Note: * Only 0 can be written, to clear the flag.
Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or
underflow and GRA or GRB compare match or input capture. These flags are interrupt sources
and generate CPU interrupts if enabled by corresponding bits in TIER.
TSR is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow.
Bit 2
OVF
Description
0
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
(Initial value)
1
[Setting condition]
TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF*
Notes: * TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow occurs
only under the following conditions:
1. Channel 2 operates in phase counting mode (MDF = 1 in TMDR)
2. Channels 3 and 4 operate in complementary PWM mode (CMD1 = 1 and CMD0 = 0 in
TFCR)
327