HD6433044 Datasheet, PDF (219/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

8.4 Operation
8.4.1 Overview
Table 8-5 summarizes the DMAC modes.
Table 8-5 DMAC Modes
Transfer Mode
Short address
mode
Full address
mode
I/O mode
Idle mode
Repeat mode
Normal mode
Block transfer mode
Activation
Compare match/input
capture A interrupt from
ITU channels 0 to 3
Transmit-data-empty
and receive-data-full
interrupts from SCI
channel 0
External request
Auto-request
External request
Compare match/input
capture A interrupt from
ITU channels 0 to 3
External request
Notes
• Up to four channels
can operate
independently
• Only the B channels
support external
requests
• A and B channels are
paired; up to two
channels are
available
• Burst mode or cycle-
steal mode can be
selected for auto-
requests
A summary of operations in these modes follows.
I/O Mode: One byte or word is transferred per request. A designated number of these transfers
are executed. A CPU interrupt can be requested at completion of the designated number of
transfers. One 24-bit address and one 8-bit address are specified. The transfer direction is
determined automatically from the activation source.
Idle Mode: One byte or word is transferred per request. A designated number of these transfers
are executed. A CPU interrupt can be requested at completion of the designated number of
transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed. The
transfer direction is determined automatically from the activation source.
Repeat Mode: One byte or word is transferred per request. A designated number of these
transfers are executed. When the designated number of transfers are completed, the initial address
and counter value are restored and operation continues. No CPU interrupt is requested. One 24-bit
address and one 8-bit address are specified. The transfer direction is determined automatically
from the activation source.
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