HD6433044 Datasheet, PDF (392/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

10.6 Usage Notes
This section describes contention and other matters requiring special attention during ITU
operations.
Contention between TCNT Write and Clear: If a counter clear signal occurs in the T₃ state of a
TCNT write cycle, clearing of the counter takes priority and the write is not performed. See
figure 10-61.
TCNT write cycle
T₁
T₂
T₃
ø
Address bus
TCNT address
Internal write signal
Figure 10-61 Contention between TCNT Write and Clear
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