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HD6433044 Datasheet, PDF (714/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer
21.4.8 DMAC Timing
DMAC timing is shown as follows.
• DMAC TEND output timing for 2 state access
Figure 21-28 shows the DMAC TEND output timing for 2 state access.
• DMAC TEND output timing for 3 state access
Figure 21-29 shows the DMAC TEND output timing for 3 state access.
• DMAC DREQ input timing
Figure 21-30 shows DMAC DREQ input timing.
ø
TEND
T1
tTED1
T2
tTED2
Figure 21-28 DMAC TEND Output Timing for 2 State Access
T1
T2
ø
tTED1
TEND
T3
tTED2
Figure 21-29 DMAC TEND Output Timing for 3 State Access
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