HD6433044 Datasheet, PDF (649/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Bits 7 to 2—Reserved: Read-only bits, always read as 1.
Bits 1 and 0—Divide (DIV1 and DIV0): These bits select the frequency division ratio, as follows.
Bit 1
DIV1
0
0
1
1
Bit 0
DIV0
0
1
0
1
Frequency Division Ratio
1/1
1/2
1/4
1/8
(Initial value)
19.5.3 Usage Notes
The DIVCR setting changes the ø frequency, so note the following points.
• Select a frequency division ratio that stays within the assured operation range specified for the
clock cycle time t_cyc in the AC electrical characteristics. Note that ø_MIN = 1 MHz. Avoid
settings that give system clock frequencies less than 1 MHz.
• All on-chip module operations are based on ø. Note that the timing of timer operations, serial
communication, and other time-dependent processing differs before and after any change in
the division ratio. The waiting time for exit from software standby mode also changes when
the division ratio is changed. For details, see section 20.4.3, Selection of Waiting Time for
Exit from Software Standby Mode.
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