HD6433044 Datasheet, PDF (429/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non-
Overlapping Output): Figure 11-7 shows an example of the use of TPC output for four-phase
complementary non-overlapping pulse output.
TCNT value
GRB
TCNT
GRA
H'0000
NDRB
95
65
59
56
95
65
Time
PBDR
00
TP₁₅
TP₁₄
TP₁₃
TP₁₂
95 05 65 41 59 50 56 14 95 05 65
Non-overlap margin
TP₁₁
TP₁₀
TP₉
TP₈
This operation example is described below.
• The output trigger ITU channel is set up so that GRA and GRB are output compare registers and the
counter will be cleared by compare match B. The TPC output trigger period is set in GRB. The non-
overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable IMFA interrupts.
• H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set
in TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is
written in NDRB.
• The timer counter in this ITU channel is started. When compare match B occurs, outputs change from
1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed
by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB.
• Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95…
at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be
obtained without loading the CPU.
Figure 11-7 Non-Overlapping TPC Output Example (Four-Phase Complementary
Non-Overlapping Pulse Output)
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