HD6433044 Datasheet, PDF (757/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

DTCR0A—Data Transfer Control Register 0A
(cont)
• Full address mode
H'27
DMAC0
Bit
Initial value
Read/Write
7
DTE
0
R/W
6
DTSZ
0
R/W
5
SAID
0
R/W
4
SAIDE
0
R/W
3
DTIE
0
R/W
2
DTS2A
0
R/W
1
DTS1A
0
R/W
0
DTS0A
0
R/W
Data transfer select 0A
0 Normal mode
1 Block transfer mode
Data transfer select 2A and 1A
Set both bits to 1
Data transfer interrupt enable
0 Interrupt request by DTE bit is disabled
1 Interrupt request by DTE bit is enabled
Source address increment/decrement (bit 5)
Source address increment/decrement enable (bit 4)
Bit 5 Bit 4
SAID SAIDE Increment/Decrement Enable
0
0 MARA is held fixed
1 Incremented: If DTSZ = 0, MARA is incremented by 1 after each transfer
If DTSZ = 1, MARA is incremented by 2 after each transfer
1
0 MARA is held fixed
1 Decremented: If DTSZ = 0, MARA is decremented by 1 after each transfer
If DTSZ = 1, MARA is decremented by 2 after each transfer
Data transfer size
0 Byte-size transfer
1 Word-size transfer
Data transfer enable
0 Data transfer is disabled
1 Data transfer is enabled
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