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HD6433044 Datasheet, PDF (123/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer
2. IRQaF flag clear and IRQbF flag generation compete (IRQaF flag setting).
(The ISR read needed for IRQaF flag clear was at IRQbF = 0 but in the time taken for ISR
write, IRQbF = 1 was reached.)
In all of the setting conditions 1 to 3 and occurrence conditions 1 and 2 are generated, IRQbF
clears in error during ISR write for occurrence condition 2 and interrupt processing is not carried
out. However, if IRQbF flag reaches 0 between occurrence conditions 1 and 2, IRQbF flag does
not clear in error.
IRQaF
IRQbF
Read Write
10
Read Write
1
0
Read Write IRQb
11
Execution
Occurrence condition 1
Read Write
0
0
Clear in error
Occurrence condition 2
Figure 5-9 IRQnF Flag When Interrupt Processing Is Not Conducted
In this situation, conduct one of the following countermeasures.
Countermeasure 1
When IRQaF flag clears, do not use the bit computation command, read the ISR in bytes. When
IRQaF only is 0 write all other bits as 1 in bytes.
For example, if a = 0
MOV.B @ISR,R0L
MOV.B #HFE,R0L
109