HD6433044 Datasheet, PDF (532/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Retransmission when SCI is in Transmit Mode (See Figure 14-12):
(6) After transmitting one frame, if the receiving device returns an error signal, the SCI sets the
ERS flag to 1 in SSR. If the RIE bit in SCR is set to the enable state, an ERI interrupt is
requested. The ERS flag should be cleared to 0 in SSR before the next parity bit sampling
timing.
(7) The TEND bit in SSR is not set for the frame in which the error signal was received,
indicating an error.
(8) If no error signal is returned from the receiving device, the ERS flag is not set in SSR.
(9) If no error signal is returned from the receiving device, transmission of the frame, including
retransmission, is assumed to be complete, and the TEND bit is set to 1 in SSR. If the TIE bit
in SCR is set to the enable state, a TXI interrupt is requested. If TXI is enabled as a DMA
transfer activation source, the next data can be written in TDR automatically. When the
DMAC writes data in TDR, it automatically clears the TDRE bit to 0.
Frame n
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransmitted frame
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Frame n + 1
Ds D0 D1 D2 D3 D4
TDRE
Transfer from TDR to TSR
TEND
ERS
Transfer from TDR to TSR
(7)
(6)
Transfer from
TDR to TSR
(9)
(8)
Figure 14-12 Retransmission in SCI Transmit Mode
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