HD6433044 Datasheet, PDF (609/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Flowchart for Erasing Multiple Blocks
Start
Write 0 data to all addresses to be
erased (prewrite)^*1
n=1
Set VPPE bit
(V_PPE bit = 1 in FLMCR)
Wait (z) µs
Set erase block registers
(set bits of blocks to be erased to 1)
Wait initial value setting x = 6.25 ms
Notes: 1. Program all addresses to be erased by
following the prewrite flowchart.
2. Set the watchdog timer overflow interval to
the value indicated in table 18-15.
3. For the erase-verify dummy write, write H'FF
with a byte transfer instruction.
4. When erasing two or more blocks, clear the
bits of erased blocks in the erase block
register, so that only unerased blocks will be
erased again.
5. t_VS1: 4 µs
z: 5 to 10 µs
Enable watchdog timer^*2
Select erase mode (E bit = 1 in FLMCR)
Wait (x) ms
Clear E bit
Disable watchdog timer
Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (t_VS1) µs
Erasing ends
t_VS2: 2 µs
N: 602
6. The erase time x is successively
incremented by the initial set value
× 2^n–1 (n = 1, 2, 3, 4). An initial
value of 10 ms or less should be
set, and the time for one erasure
should be 50 ms or less.
Erase-verify
next block
Set top address of block as
verify address
Dummy write to verify address^*3
(flash memory latches address)
Wait (t_VS2) µs
No
Address + 1 → address
Verify
(read memory)
OK
Last
address in block?
No good
Yes
Clear EBR bit of erase-verified block ^*4
Erase-verify next block
All erased blocks
No
verified?
Yes
No
All erased blocks
verified?
Yes
Clear EV bit
All blocks erased?
No
(EBR1 = EBR2 = 0?)
Yes
Clear V_PPE bit
n ≥ 4?
Yes
No
Double the erase time (x × 2 → x)
End of erase
No
n ≥ N?
Yes
Clear erase block registers
(clear bits of blocks to be erased to 0)
Clear V_PPE bit
Erase error
n+1→n
Figure 18-18 Multiple-Block Erase Flowchart
600