HD6433044 Datasheet, PDF (828/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

BRCR—Bus Release Control Register
H'F3
Bus controller
Bit
7
A23E
Modes _{Initial value 1}
1, 2,
5, 7 ^{Read/Write —}
Modes ^{Initial value 1}
3, 4, 6 _{Read/Write R/W}
6
A22E
1
—
1
R/W
5
4
3
2
1
0
A21E
—
—
—
—
BRLE
1
1
1
1
1
0
—
—
—
—
—
R/W
1
1
1
1
1
0
R/W
—
—
—
—
R/W
Bus release enable
0 The bus cannot be released to an external device
1 The bus can be released to an external device
Address 23 to 21 enable
0 Address output
1 Other input/output
ISCR—IRQ Sense Control Register
H'F4 Interrupt controller
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
—
— IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
0
0
0
0
0
0
0
0
R/W
R/W R/W
R/W R/W
R/W R/W R/W
IRQ₅ to IRQ₀ sense control
0 Interrupts are requested when IRQ₅ to IRQ₀ inputs are low
1 Interrupts are requested by falling-edge input at IRQ₅ to IRQ₀
IER—IRQ Enable Register
H'F5 Interrupt controller
Bit
Initial value
Read/Write
7
—
0
R/(W)
6
—
0
R/(W)
5
IRQ5E
0
R/(W)
4
IRQ4E
0
R/(W)
3
IRQ3E
0
R/(W)
2
IRQ2E
0
R/(W)
1
IRQ1E
0
R/(W)
0
IRQ0E
0
R/(W)
IRQ₅ to IRQ₀ enable
0 IRQ ₅ to IRQ₀ interrupts are disabled
1 IRQ ₅ to IRQ₀ interrupts are enabled
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