HD6433044 Datasheet, PDF (578/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

18.4 Flash Memory Overview
18.4.1 Flash Memory Operation
Table 18-7 illustrates the principle of operation of the H8/3048F’s on-chip flash memory.
Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws
hot electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a
programmed memory cell is therefore higher than that of an erased cell. Cells are erased by
grounding the gate and applying a high voltage to the source, causing the electrons stored in the
floating gate to tunnel out. After erasure, the threshold voltage drops. A memory cell is read like
an EPROM cell, by driving the gate to the high level and detecting the drain current, which
depends on the threshold voltage. Erasing must be done carefully, because if a memory cell is
overerased, its threshold voltage may become negative, causing the cell to operate incorrectly.
Section 18.7.6, Erasing Flowchart and Sample Program shows an optimal erase control flowchart
and sample program.
Table 18-7 Principle of Memory Cell Operation
Memory
cell
Program
Vg = V_PP
Vd
Erase
Vg = V_PP
Vd
Read
Vg = V_PP
Vd
Memory
array
Vg = V_PP
Vd
Vg = V_PP
Vd
Vd
0V
Vg = V_PP
Vd
Vd
0V
Vd
0V
Vd
0V
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