HD6433044 Datasheet, PDF (63/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Exception
sources
Reset
Interrupt
Trap instruction
External interrupts
Internal interrupts (from on-chip supporting modules)
Figure 2-12 Classification of Exception Sources
End of bus release
Bus request
End of bus
Program execution state
release
Bus
request
Exception
SLEEP
instruction
with SSBY = 0
Bus-released state
Sleep mode
End of
exception
handling
Exception-handling state
Interrupt
NMI, IRQ₀, IRQ ₁,
or IRQ ₂ interrupt
SLEEP instruction
with SSBY = 1
Software standby mode
RES = 1
Reset state^*1
STBY = 1, RES = 0
Hardware standby mode^*2
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2-13 State Transitions
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