HD6433044 Datasheet, PDF (224/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Table 8-7 Register Functions in Idle Mode
Register
23
0
MAR
23
All 1s
7
0
IOAR
15
0
Decremented _ETCR
Function
Activated by
SCI 0 Receive-
Data-Full
Other
Interrupt
Activation
Initial Setting
Destination
address
register
Source
address
register
Destination or
source address
Source
address
register
Destination Source or
address destination
register
address
Transfer counter
transfers
Legend
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Operation
Held fixed
Held fixed
Number of
once per
transfer until
H'0000 is
reached and
transfer ends
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all
1s. MAR and IOAR are not incremented or decremented.
Figure 8-4 illustrates how idle mode operates.
MAR
Transfer
1 byte or word is
transferred per request
Figure 8-4 Operation in Idle Mode
210
IOAR