HD6433044 Datasheet, PDF (142/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Bus cycle
T₁
T₂
T₃
ø
Address bus
CS _n
AS
RD
Read
access
D₁₅ to D₈
D₇ to D ₀
HWR
Write
access
LWR
D₁₅ to D₈
D₇ to D ₀
Note: n = 7 to 0
High
Odd external address in area n
Invalid
Valid
Undetermined data
Valid
Figure 6-7 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
(Byte Access to Odd Address)
128