HD6433044 Datasheet, PDF (159/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

DDR Write Timing: Data written to a data direction register (DDR) to change a CS_n pin from
CS_n output to generic input, or vice versa, takes effect starting from the T₃ state of the DDR write
cycle. Figure 6-21 shows the timing when the CS₁ pin is changed from generic input to CS₁
output.
ø
Address
bus
CS₁
T₁
T₂
T₃
P8DDR address
High impedance
Figure 6-21 DDR Write Timing
BRCR Write Timing: Data written to switch between A₂₃, A₂₂, or A₂₁ output and generic input
or output takes effect starting from the T₃ state of the BRCR write cycle. Figure 6-22 shows the
timing when a pin is changed from generic input to A₂₃, A₂₂, or A₂₁ output.
ø
Address
bus
A ₂₃ to A ₂₁
T₁
T₂
T₃
BRCR address
High impedance
Figure 6-22 BRCR Write Timing
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