HD6433044 Datasheet, PDF (709/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

21.4.3 Control Signal Timing
Control signal timing is shown as follows:
• Reset input timing
Figure 21-18 shows the reset input timing.
• Reset output timing
Figure 21-19 shows the reset output timing.
• Interrupt input timing
Figure 21-20 shows the input timing for NMI and IRQ₅ to IRQ₀.
• Bus-release mode timing
Figure 21-21 shows the bus-release mode timing.
ø
RES
MD2 to MD0
t_RESS
t_MDS
t_RESS
t_RESW
Figure 21-18 Reset Input Timing
ø
RESO
t_RESD
t_RESD
t_RESOW
Figure 21-19 Reset Output Timing
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