HD6433044 Datasheet, PDF (692/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Table 21-12 Bus Timing (cont)
Condition A: V_CC = 2.7 V to 5.5 V, AV_CC = 2.7 V to 5.5 V, V_REF = 2.7 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 1 MHz to 8 MHz, T_a = –20°C to +75°C (regular
specifications), T_a = –40°C to +85°C (wide-range specifications)
Condition C: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_REF = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 1 MHz to 16 MHz, T_a = –20°C to +75°C (regular
specifications), T_a = –40°C to +85°C (wide-range specifications)
Condition A
Condition C
8 MHz
16 MHz
Item
Symbol Min
Max
Min
Max Unit
Write data delay time
t_WDD
—
75
—
60
ns
Write data setup time 1
t_WDS1
60
—
15
—
Write data setup time 2
t_WDS2
5
—
–5
—
Write data hold time
t_WDH
25
—
20
—
Read data access time 1
t_ACC1*
—
120
—
60
Read data access time 2
t_ACC2*
—
240
—
120
Read data access time 3
t_ACC3*
—
70
—
30
Read data access time 4
t_ACC4*
—
180
—
95
Precharge time
t_PCH*
85
—
45
—
Wait setup time
t_WTS
40
—
25
—
ns
Wait hold time
t_WTH
10
—
5
—
Bus request setup time
t_BRQS
40
—
40
—
ns
Bus acknowledge delay time 1 t_BACD1
—
60
—
30
Bus acknowledge delay time 2 t_BACD2
—
60
—
30
Bus-floating time
t_BZD
—
70
—
40
Note: At 8 MHz, the times below depend as indicated on the clock cycle time.
t_ACC1 = 1.5 × t_CYC – 68 (ns)
t_WSW1 = 1.0 × t_CYC – 40 (ns)
t_ACC2 = 2.5 × t_CYC – 73 (ns)
t_WSW2 = 1.5 × t_CYC – 38 (ns)
t_ACC3 = 1.0 × t_CYC – 55 (ns)
t_PCH = 1.0 × t_CYC – 40 (ns)
t_ACC4 = 2.0 × t_CYC – 70 (ns)
At 16 MHz, the times below depend as indicated on the clock cycle time.
t_ACC1 = 1.5 × t_CYC – 34 (ns)
t_ACC2 = 2.5 × t_CYC – 37 (ns)
t_ACC3 = 1.0 × t_CYC – 33 (ns)
t_ACC4 = 2.0 × t_CYC – 30 (ns)
t_WSW1 = 1.0 × t_CYC – 28 (ns)
t_WSW2 = 1.5 × t_CYC – 29 (ns)
t_PCH = 1.0 × t_CYC – 28 (ns)
Test
Conditions
Figure 21-7
Figure 21-8
Figure 21-9
Figure 21-21
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