HD6433044 Datasheet, PDF (648/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

19.3 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the signal that becomes the system clock.
19.4 Prescalers
The prescalers divide the system clock (ø) to generate internal clocks (ø/2 to ø/4096).
19.5 Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (ø). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
ø pin.
19.5.1 Register Configuration
Table 19-4 summarizes the frequency division register.
Table 19-4 Frequency Division Register
Address*
Name
Abbreviation
H'FF5D
Division control register
DIVCR
Note: * The lower 16 bits of the address are shown.
R/W
Initial Value
R/W
H'FC
19.5.2 Division Control Register (DIVCR)
DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
DIV1 DIV0
Initial value
1
1
1
1
1
1
0
0
Read/Write
—
—
—
—
—
—
R/W R/W
Reserved bits
Divide bits 1 and 0
These bits select the
frequency division ratio
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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