HD6433044 Datasheet, PDF (829/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

ISR—IRQ Status Register
Bit
7
6
—
—
Initial value
0
0
Read/Write
—
—
H'F6 Interrupt controller
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
0
IRQ0F
0
R/(W)*
IRQ₅ to IRQ ₀ flags
Bits 5 to 0
IRQ5F to IRQ0F Setting and Clearing Conditions
0
[Clearing conditions]
Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
IRQnSC = 0, IRQn input is high, and interrupt exception
handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is
carried out.
1
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and a falling edge is generated in the IRQn input.
(n = 5 to 0)
Note: * Only 0 can be written, to clear the flag.
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