HD6433044 Datasheet, PDF (856/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Appendix D Pin States
D.1 Port States in Each Mode
Table D-1 Port States
Pin
Name
Mode
Reset
Hardware Software Bus-
Standby Standby Released
Mode
Mode
Mode
Program
Execution,
Sleep Mode
ø
—
Clock output T
H
Clock output Clock output
RESO
—
T*
T
T
T
RESO
P1₇ to P1₀ 1 to 4
5, 6
L
T
T
T
A₇ to A₀
T
T
keep
T
Input port
(DDR = 0)
T
T
A₇ to A₀
(DDR = 1)
7
T
T
keep
—
I/O port
P2₇ to P2₀ 1 to 4
5, 6
L
T
T
T
A₁₅ to A₈
T
T
keep
T
Input port
(DDR = 0)
T
T
A₁₅ to A₈
(DDR = 1)
7
T
T
keep
—
I/O port
P3₇ to P3₀ 1 to 6
7
T
T
T
T
D₁₅ to D₈
T
T
keep
—
I/O port
P4₇ to P4₀
1 to 6 8-bit bus T
16-bit bus T
7
T
T
keep
keep
I/O port
T
T
T
T
keep
—
D₇ to D₀
I/O port
Legend
H: High
L: Low
T: High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
Note: * Low output only when WDT overflow causes a reset.
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