HD6433044 Datasheet, PDF (192/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the
T₃ state of an RTCNT write cycle, clearing of the counter takes priority and the write is not
performed. See figure 7-20.
ø
Address bus
Internal
write signal
Counter
clear signal
RTCNT
RTCNT write cycle by CPU
T₁
T₂
T₃
RTCNT address
N
H'00
Figure 7-20 Contention between RTCNT Write and Clear
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