HD6433044 Datasheet, PDF (421/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits
select the compare match event that triggers TPC output group 1 (TP₇ to TP₄).
Bit 3
Bit 2
G1CMS1 G1CMS0 Description
0
0
TPC output group 1 (TP₇ to TP₄) is triggered by compare match in ITU
channel 0
1
TPC output group 1 (TP₇ to TP₄) is triggered by compare match in ITU
channel 1
1
0
TPC output group 1 (TP₇ to TP₄) is triggered by compare match in ITU
channel 2
1
TPC output group 1 (TP₇ to TP₄) is triggered by
compare match in ITU channel 3
(Initial value)
Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits
select the compare match event that triggers TPC output group 0 (TP₃ to TP₀).
Bit 1
G0CMS1
0
1
Bit 0
G0CMS0
0
1
0
1
Description
TPC output group 0 (TP₃ to TP₀) is triggered by compare match in ITU
channel 0
TPC output group 0 (TP₃ to TP₀) is triggered by compare match in ITU
channel 1
TPC output group 0 (TP₃ to TP₀) is triggered by compare match in ITU
channel 2
TPC output group 0 (TP₃ to TP₀) is triggered by
compare match in ITU channel 3
(Initial value)
409