HD6433044 Datasheet, PDF (403/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Table 10-11 (b) ITU Operating Modes (Channel 1)
Register Settings
TSNC
TMDR
TFCR
TOCR
TOER
TIOR1
TCR1
Reset-
Comple- Synchro-
Output
Synchro-
mentary nized Buffer-
Level Master
Clear
Clock
Operating Mode
nization MDF FDIR PWM
PWM PWM ing XTGD Select Enable IOA
IOB
Select
Select
Synchronous preset SYNC1 = 1 —
—
—
—
—
—
—
—
PWM mode
—
— PWM1 = 1 —
—
—
—
—
—
—
*1
Output compare A
—
— PWM1 = 0 —
—
—
—
—
—
IOA2 = 0
Other bits
unrestricted
Output compare B
—
—
—
—
—
—
—
—
IOB2 = 0
Other bits
unrestricted
Input capture A
—
— PWM1 = 0 —
—
—
*2
—
—
IOA2 = 1
Other bits
unrestricted
Input capture B
—
— PWM1 = 0 —
—
—
—
—
—
IOB2 = 1
Other bits
unrestricted
Counter By compare
clearing match/input
capture A
—
—
—
—
—
—
—
—
CCLR1 = 0
CCLR0 = 1
By compare
match/input
capture B
—
—
—
—
—
—
—
—
CCLR1 = 1
CCLR0 = 0
Syn-
SYNC1 = 1 —
—
chronous
clear
—
—
—
—
—
—
CCLR1 = 1
CCLR0 = 1
Legend: Setting available (valid). — Setting does not affect this mode.
Notes: 1. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
2. Valid only when channels 3 and 4 are operating in complementary PWM mode or reset-synchronized PWM mode.