HD6433044 Datasheet, PDF (440/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip
internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to
initialize external system devices.
Bit 7
WRST
0
1
Description
[Clearing conditions]
Cleared to 0 by reset signal input at RES pin
Cleared by reading WRST when WRST = 1, then writing 0 in WRST
(Initial value)
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of
the reset signal generated if TCNT overflows during watchdog timer operation.
Bit 6
RSTOE Description
0
Reset signal is not output externally
1
Reset signal is output externally
(Initial value)
Bits 5 to 0—Reserved: Read-only bits, always read as 1.
428