HD6433044 Datasheet, PDF (604/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

18.7.6 Erasing Flowchart and Sample Program
Flowchart for Erasing One Block
Start
Write 0 data in all addresses
to be erased (prewrite)^*1
n=1
Set V_PPE bit
(V_PPE bit = 1 in FLMCR)
Wait (z) µs
Set erase block register
(set bit of block to be erased to 1)
Set top address in block
as verify address
Wait initial value setting x = 6.25 ms
Enable watchdog timer^*2
Select erase mode
(E bit = 1 in FLMCR)
Wait (x) ms
Clear E bit
Disable watchdog timer
Notes: 1. Program all addresses to be
erased by following the prewrite
flowchart.
2. Set the watchdog timer overflow
interval to the value indicated in
table 18-15.
3. For the erase-verify dummy
write, write H'FF using a byte
transfer instruction.
4. Read to verify data from the
memory using a byte transfer
instruction.
5. t_VS1: 4 µs
z: 5 to 10 µs
t_VS2: 2 µs
N: 602
6. The erase time x is successively
incremented by the initial set
value × 2^n–1 (n = 1, 2, 3, 4). An
initial value of 6.25 ms or less
should be set, and the time for
Erasing ends
one erasure should be 50 ms or
less.
Select erase-verify mode
(EV bit = 1)
Wait (t_VS1) µs
Dummy write to verify address^*3
(flash memory latches address)
Wait (t_VS2) µs
No
Address + 1 → address
Verify (read memory)^*4
OK
Last address?
Yes
Clear EV bit
Clear erase block register
(clear bit of erased block to 0)
Clear V_PPE bit
End of block erase
No good
Clear EV bit
Erase-verify ends
No
n ≥ N?
Yes
Clear erase block register
(clear bit of block to be
erased to 0)
Clear V_PPE bit
Erase error
n + 1→ n
Yes
n ≥ 5?
No
Double the erase time
(x × 2 → x)
Figure 18-16 Erasing Flowchart
595