HD6433044 Datasheet, PDF(241/867 Page) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HD6433044 Datasheet, PDF (241/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

◁

Figure 8-15 shows an auto-requested burst-mode transfer. This example shows a transfer of three

words from a 16-bit two-state access area to another 16-bit two-state access area.

CPU cycle

DMAC cycle

CPU cyc

T1 T2 Td T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2

Ã¸

Address

bus

RD

Source Destination

address address

HWR,

LWR

Figure 8-15 Burst DMA Bus Timing

When the DMAC is activated from a DREQ pin there is a minimum interval of four states from

when the transfer is requested until the DMAC starts operating. The DREQ pin is not sampled

during the time between the transfer request and the start of the transfer. In short address mode

and normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the

pin is next sampled at the end of one block transfer.

227

▷