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| HD6433044 Datasheet, PDF (20/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer | |||
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1.2 Block Diagram
Figure 1-1 shows an internal block diagram.
MD 2
MD 1
MD 0
EXTAL
XTAL
ø
STBY
RES
VPP */RESO
NMI
P66 /LWR
P65 /HWR
P64 /RD
P63 /AS
P6 2/BACK
P61/BREQ
P60/WAIT
P84 /CS0
P83/CS1 /IRQ3
P82/CS2 /IRQ2
P81/CS3 /IRQ1
P80 /RFSH/IRQ 0
Port 3
Address bus
Data bus (upper)
Data bus (lower)
Port 4
H8/300H CPU
Interrupt controller
ROM
(masked ROM,
PROM, or flash
memory)
RAM
16-bit integrated
timer unit
(ITU)
Programmable
timing pattern
controller (TPC)
DMA controller
(DMAC)
Refresh
controller
Watchdog timer
(WDT)
Serial communication
interface
(SCI) Ã 2 channels
A/D converter
D/A converter
Port B
Port A
Port 7
P53 /A 19
P52 /A 18
P51 /A 17
P50 /A 16
P27/A 15
P26/A 14
P25/A 13
P24/A 12
P23/A 11
P22/A 10
P21/A 9
P20/A 8
P17/A 7
P16/A 6
P15/A 5
P14/A 4
P13/A 3
P12/A 2
P11/A 1
P10/A 0
P95/SCK1/IRQ5
P94/SCK0/IRQ4
P93/RxD1
P92/RxD0
P91/TxD 1
P90/TxD 0
Note: * VPP function is provided only for the flash memory version.
Figure 1-1 Block Diagram
5
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