HD6433044 Datasheet, PDF (859/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

D.2 Pin States at Reset
Reset in T1 State: Figure D-1 is a timing diagram for the case in which RES goes low during the
T1 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance
state. The address bus is initialized to the low output level 0.5 state after the low level of RES is
sampled. Sampling of RES takes place at the fall of the system clock (ø).
Access to external address
T1
T2
T3
ø
RES
Internal
reset signal
Address bus
H'000000
CS₀
CS₇ to CS₁
AS
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
High
High
High
High impedance
High impedance
High impedance
Figure D-1 Reset during Memory Access (Reset during T1 State)
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