HD6433044 Datasheet, PDF (209/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 3
DTIE
0
1
Description
The DEND interrupt requested by DTE is disabled
The DEND interrupt requested by DTE is enabled
(Initial value)
Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer
activation source. Some of the selectable sources differ between channels A and B.*
Note: * Refer to 8-3-4, Data Transfer Control Registers (DTCR).
Bit 2
DTS2
0
1
Bit 1
DTS1
0
1
0
1
Bit 0
DTS0
0
1
0
1
0
1
0
1
Description
Compare match/input capture A interrupt from ITU
channel 0
(Initial value)
Compare match/input capture A interrupt from ITU channel 1
Compare match/input capture A interrupt from ITU channel 2
Compare match/input capture A interrupt from ITU channel 3
Transmit-data-empty interrupt from SCI channel 0
Receive-data-full interrupt from SCI channel 0
Falling edge of DREQ input (channel B)
Transfer in full address mode (channel A)
Low level of DREQ input (channel B)
Transfer in full address mode (channel A)
The same internal interrupt can be selected as an activation source for two or more channels at
once. In that case the channels are activated in a priority order, highest-priority channel first. For
the priority order, see section 8.4.9, Multiple-Channel Operation.
When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a
CPU interrupt.
195