HD6433044 Datasheet, PDF (243/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Figure 8-17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in
normal mode.
CPU cycle
DMAC cycle
CPU cycle
T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T ₁
ø
DREQ
Address
bus
RD
HWR , LWR
Minimum 4 states
Next sampling point
Figure 8-17 Timing of DMAC Activation by Low DREQ Level in Normal Mode
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