HD6433044 Datasheet, PDF (620/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

18.8 Flash Memory Emulation by RAM
Erasing and programming flash memory takes time, which can make it difficult to tune parameters
and other data in real time. If necessary, real-time updates of flash memory can be emulated by
overlapping the small-block flash-memory area with part of the RAM (H'FFF000 to H'FFF1FF).
This RAM reassignment is performed using bits 3 to 0 of the RAM control register (RAMCR).
After a flash memory area has been overlapped by RAM, it can be accessed from two address
areas: the overlapped flash memory area, and the original RAM area (H'FFF000 to H'FFF1FF).
Table 18-16 indicates how to reassign RAM.
RAM Control Register (RAMCR)
Bit
7
6
5
FLER —
—
Initial value^* 0
1
1
R/W
R
—
—
4
3
2
1
0
— RAMS RAM2 RAM1 RAM0
1
0
0
0
0
—
R/W R/W R/W R/W
Note: * Bit 7 and bits 3 to 0 are initialized by a reset and in hardware standby mode. They are
not initialized in software standby mode.
Table 18-16 RAM Area Reassignment
RAM Area
H'FFF000 to H'FFF1FF
H'01F000 to H'01F1FF
H'01F200 to H'01F3FF
H'01F400 to H'01F5FF
H'01F600 to H'01F7FF
H'01F800 to H'01F9FF
H'01FA00 to H'01FBFF
H'01FC00 to H'01FDFF
H'01FE00 to H'01FFFF
Bit 3
RAMS
0
1
1
1
1
1
1
1
1
Bit 2
RAM2
0/1
0
0
0
0
1
1
1
1
Bit 1
RAM1
0/1
0
0
1
1
0
0
1
1
Bit 0
RAM0
0/1
0
1
0
1
0
1
0
1
611