HD6433044 Datasheet, PDF (662/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

20.7 System Clock Output Disabling Function
Output of the system clock (ø) can be controlled by the PSTOP bit in MSTCR. When the PSTOP
bit is set to 1, output of the system clock halts and the ø pin is placed in the high-impedance state.
Figure 20-3 shows the timing of the stopping and starting of system clock output. When the
PSTOP bit is cleared to 0, output of the system clock is enabled. Table 20-4 indicates the state of
the ø pin in various operating states.
MSTCR write cycle
(PSTOP = 1)
MSTCR write cycle
(PSTOP = 0)
ø pin
T1 T2 T3
High impedance
T1 T2 T3
Figure 20-3 Starting and Stopping of System Clock Output
Table 20-4 ø Pin State in Various Operating States
Operating State
Hardware standby
Software standby
Sleep mode
Normal operation
PSTOP = 0
High impedance
Always high
System clock output
System clock output
PSTOP = 1
High impedance
High impedance
High impedance
High impedance
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