HD6433044 Datasheet, PDF (516/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

TxD₀
RxD₀
SCK₀
Px (port)
H8/3048 Series
Chip
Card-processing device
V_CC
Data line
Clock line
Reset line
I/O
CLK
RST
Smart card
Figure 14-2 Smart Card Interface Connection Diagram
Note: A loop-back test can be performed by setting both RE and TE to 1 without connecting a
smart card.
14.3.3 Data Format
Figure 14-3 shows the data format of the smart card interface. In receive mode, parity is checked
once per frame. If a parity error is detected, an error signal is returned to the transmitting device to
request retransmission. In transmit mode, the error signal is sampled and the same data is
retransmitted if the error signal is low.
No parity error
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Output from transmitting device
Parity error
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Output from transmitting device
Ds:
Start bit
D0 to D7: Data bits
Dp:
Parity bit
DE:
Error signal
Output from
receiving device
Figure 14-3 Smart Card Interface Data Format
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