HD6433044 Datasheet, PDF (602/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

CMP.B R3H,
R1H
; Compare programmed data with read data
BEQ
PVOK
; Program-verify decision
PVNG: MOV.B #40,
R5H
;
MOV.B R5H,
@FLMCR:8 ; Clear PV bit
CMP.B #06,
R0L
; Program-verify executed 6 times?
BEQ
NGEND
; If program-verify executed 6 times, branch
to NGEND
INC.B R0L
; Program-verify fail count + 1 → R0L
SHLL.W E4
; Double program loop counter value
BRA
PRGMS
; Program again
PVOK: MOV.W #4000, R5
;
MOV.B R5H,
@FLMCR:8 ; Clear PV bit
MOV.B R5L,
@EBR*:8 ;Clear EBR*
MOV.B R5L,
@FLMCR:8 ;Clear V_PPE bit
. . . . . . . . . . . . . . . . . . One byte programmed
NGEND: MOV.W #4000, R5
;
MOV.B R5L,
@EBR*:8 ;Clear EBR*
MOV.B R5L,
Programming error
@FLMCR:8 ;Clear V_PPE bit
18.7.4 Erase Mode
To erase the flash memory, follow the erasing algorithm shown in figure 18-16. This erasing
algorithm can erase data without subjecting the device to voltage stress or impairing the reliability
of programmed data.
To erase flash memory, before starting to erase, first place all memory data in all blocks to be
erased in the programmed state (program all memory data to H'00). If all memory data is not in
the programmed state, follow the sequence described later to program the memory data to zero.
To select the flash memory areas to be erased, first set the V_PPE bit in the flash memory control
register (FLMCR), wait 5 to 10 µs, and set up erase block registers 1 and 2 (EBR1 and EBR2).
Next set the E bit in FLMCR, selecting erase mode. The erase time is the time during which the
E bit is set. To prevent overerasing, use a software timer to divide the erase time. Overerasing,
due to program runaway for example, can give memory cells a negative threshold voltage and
cause them to operate incorrectly. Before selecting erase mode, set up the watchdog timer so as to
prevent overerasing.
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