HD6433044 Datasheet, PDF (621/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Example of Emulation of Real-Time Flash-Memory Update
H'01F000
Small-block
area (SB5)
H'01F9FF
H'01FA00
H'01FBFF
H'01FDFF
H'01FE00
H'01FFFF
Procedure
Flash memory
address space
1. Set the RAME bit to 1 in SYSCR
to enable the on-chip RAM.
Overlapped by RAM
2. Overlap part of RAM (H'FFF000 to
H'FFF1FF) onto the area requiring
real-time update (SB5).
(Set RAMCR bits 3 to 0 to 1101.)
3. Perform real-time updates in the
overlapping RAM.
4. After finalization of the update
data, clear the RAM overlap (by
clearing the RAMS bit).
H'FFEF10
H'FFF000
H'FFF1FF
H'FFF200
H'FFFF0F
On-chip RAM
area
5. Program the data written in RAM
addresses H'FFF000 to H'FFF1FF
into the flash memory area.
Notes: 1. When part of RAM (H'FFF000 to H'FFF1FF) is overlapped onto a small-block area in flash
memory, the overlapped flash memory area cannot be accessed. Access is enabled when
the overlap is cleared.
2. When the RAMS bit is set to 1, all flash memory blocks are write-protected and erase-
protected, regardless of the values of bits RAM2 to RAM0. In this state, no transition to
program or erase mode will take place if the P or E bit is set in the flash memory control
register (FLMCR). To actually program or erase a flash memory area, the RAMS bit must
be cleared to 0.
Figure 18-20 Example of RAM Overlap
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