HD6433044 Datasheet, PDF (137/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

6.3.2 Chip Select Signals
For each of areas 0 to 7, the H8/3048 Series can output a chip select signal (CS₀ to CS₇) that goes
low to indicate when the area is selected. Figure 6-3 shows the output timing of a CS_n signal
(n = 0 to 7).
Output of CS₀ to CS₃: Output of CS₀ to CS₃ is enabled or disabled in the data direction register
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS₀ in the output state and
pins CS₁ to CS₃ in the input state. To output chip select signals CS₁ to CS₃, the corresponding
DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins
CS₀ to CS₃ in the input state. To output chip select signals CS₀ to CS₃, the corresponding DDR
bits must be set to 1. For details see section 9, I/O Ports.
Output of CS₄ to CS₇: Output of CS₄ to CS₇ is enabled or disabled in the chip select control
register (CSCR). A reset leaves pins CS₄ to CS₇ in the input state. To output chip select signals
CS₄ to CS₇, the corresponding CSCR bits must be set to 1. For details see section 9, I/O Ports.
ø
Address
bus
CS_n
External address in area n
Figure 6-3 CS_n Output Timing (n = 0 to 7)
When the on-chip ROM, on-chip RAM, and on-chip registers are accessed, CS₀ and CS₇ remain
high. The CS_n signals are decoded from the address signals. They can be used as chip select
signals for SRAM and other devices.
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