HD6433044 Datasheet, PDF (338/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Bit 3—Reserved: Read-only bit, always read as 1.
Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
Function
0
0
0
GRA is an output No output at compare match (Initial value)
1
compare register _{0 output at GRA compare match*1}
1
0
1 output at GRA compare match^*1
1
Output toggles at GRA compare match
(1 output in channel 2)^{*1, *2}
1
0
0
GRA is an input GRA captures rising edge of input
1
capture register
GRA captures falling edge of input
1
0
GRA captures both edges of input
1
Notes: 1. After a reset, the output is 0 until the first compare match.
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
instead.
10.2.12 Timer Status Register (TSR)
TSR is an 8-bit register. The ITU has five TSRs, one in each channel.
Channel
0
1
2
3
4
Abbreviation
TSR0
TSR1
TSR2
TSR3
TSR4
Function
Indicates input capture, compare match, and overflow status
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