HD6433044 Datasheet, PDF (27/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Table 1-3 Pin Functions (cont)
Type
Refresh
controller
DMA
controller
(DMAC)
16-bit
integrated
timer unit
(ITU)
Symbol
RFSH
Pin No.
87
I/O Name and Function
Output Refresh: Indicates a refresh cycle
CS₃
RD
HWR
LWR
DREQ₁,
DREQ₀
TEND₁,
TEND₀
TCLKD to
TCLKA
TIOCA₄ to
TIOCA₀
TIOCB₄ to
TIOCB₀
TOCXA₄
TOCXB₄
88
70
71
72
9, 8
94, 93
96 to 93
4, 2, 99,
97, 95
5, 3, 100,
98, 96
6
7
Output Row address strobe RAS: Row address
strobe signal for DRAM connected to area 3
Output Column address strobe CAS: Column
address strobe signal for DRAM connected to
area 3; used with 2WE DRAM.
Write enable WE: Write enable signal for
DRAM connected to area 3; used with 2CAS
DRAM.
Output Upper write UW: Write enable signal for
DRAM connected to area 3; used with 2WE
DRAM.
Upper column address strobe UCAS:
Column address strobe signal for DRAM
connected to area 3; used with 2CAS DRAM.
Output Lower write LW: Write enable signal for DRAM
connected to area 3; used with 2WE DRAM.
Lower column address strobe LCAS:
Column address strobe signal for DRAM
connected to area 3; used with 2CAS DRAM.
Input DMA request 1 and 0: DMAC activation
requests
Output Transfer end 1 and 0: These signals indicate
that the DMAC has ended a data transfer
Input Clock input D to A: External clock inputs
Input/ Input capture/output compare A4 to A0:
output GRA4 to GRA0 output compare or input
capture, or PWM output
Input/ Input capture/output compare B4 to B0:
output GRB4 to GRB0 output compare or input
capture, or PWM output
Output Output compare XA4: PWM output
Output Output compare XB4: PWM output
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