HD6433044 Datasheet, PDF (132/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

6.2.5 Bus Release Control Register (BRCR)
BRCR is an 8-bit readable/writable register that enables address output on bus lines A₂₃ to A₂₁
and enables or disables release of the bus to an external device.
Bit
7
A23E
Initial value
1
Read/ ^{Mode 1, 2, 5, 7 —}
Write _{Mode 3, 4, 6 R/W}
6
A22E
1
—
R/W
5
A21E
1
—
R/W
Address 23 to 21 enable
These bits enable PA ₆ to
PA ₄ to be used for A ₂₃ to
A ₂₁ address output
4
3
2
1
0
—
—
—
— BRLE
1
1
1
1
0
—
—
—
—
R/W
—
—
—
—
R/W
Reserved bits
Bus release enable
Enables or disables
release of the bus to
an external device
BRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Address 23 Enable (A23E): Enables PA₄ to be used as the A₂₃ address output pin.
Writing 0 in this bit enables A₂₃ address output from PA₄. In modes other than 3, 4, and 6 this bit
cannot be modified and PA₄ has its ordinary input/output functions.
Bit 7
A23E Description
0
PA₄ is the A₂₃ address output pin
1
PA₄ is the PA₄/TP₄/TIOCA₁ input/output pin
(Initial value)
Bit 6—Address 22 Enable (A22E): Enables PA₅ to be used as the A₂₂ address output pin.
Writing 0 in this bit enables A₂₂ address output from PA₅. In modes other than 3, 4, and 6 this bit
cannot be modified and PA₅ has its ordinary input/output functions.
Bit 6
A22E
0
1
Description
PA₅ is the A₂₂ address output pin
PA₅ is the PA₅/TP₅/TIOCB₁ input/output pin
(Initial value)
118