HD6433044 Datasheet, PDF (693/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

Table 21-13 Refresh Controller Bus Timing
Condition A: V_CC = 2.7 V to 5.5 V, AV_CC = 2.7 V to 5.5 V, V_REF = 2.7 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 1 MHz to 8 MHz, T_a = –20°C to +75°C (regular
specifications), T_a = –40°C to +85°C (wide-range specifications)
Condition C: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_REF = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 1 MHz to 16 MHz, T_a = –20°C to +75°C (regular
specifications), T_a = –40°C to +85°C (wide-range specifications)
Condition A
Condition C
8 MHz
16 MHz
Item
Symbol Min
Max
Min
Max Unit
RAS delay time 1
t_RAD1
—
60
—
30
ns
RAS delay time 2
t_RAD2
—
60
—
30
RAS delay time 3
t_RAD3
—
60
—
30
Row address hold time*
t_RAH
25
—
15
—
RAS precharge time*
t_RP
85
—
45
—
CAS to RAS precharge time*
t_CRP
85
—
45
—
CAS pulse width
t_CAS
100
—
40
—
RAS access time*
t_RAC
—
160
—
85
Address access time
t_AA
—
105
—
55
CAS access time*
t_CAC
—
50
—
30
Write data setup time 3
t_WDS3
50
—
15
—
CAS setup time*
t_CSR
20
—
15
—
Read strobe delay time
t_RSD
—
60
—
30
Note: At 8 MHz, the times below depend as indicated on the clock cycle time.
t_RAH = 0.5 × t_CYC – 38 (ns)
t_CAC = 1.0 × t_CYC – 75 (ns)
t_RAC = 2.0 × t_CYC – 90 (ns)
t_CSR = 0.5 × t_CYC – 43 (ns)
t_RP = t_CRP = 1.0 × t_CYC – 40 (ns)
At 16 MHz, the times below depend as indicated on the clock cycle time.
t_RAH = 0.5 × t_CYC – 17 (ns)
t_RAC = 2.0 × t_CYC – 40 (ns)
t_RP = t_CRP = 1.0 × t_CYC – 18 (ns)
t_CAC = 1.0 × t_CYC – 33 (ns)
t_CSR = 0.5 × t_CYC – 17 (ns)
Test
Conditions
Figure 21-10
to
Figure 21-16
685