HD6433044 Datasheet, PDF (521/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

The following equation calculates the bit rate register (BRR) setting from the system clock
frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error.
ø
N=
× 10⁶ – 1
1488 × 2^2n–1 × B
Table 14-6 BRR Settings for Typical Bit Rate (bits/s) (when n = 0)
7.1424
Bit/s N Error
9600 0 0.00
10.00
N Error
1 30.00
10.7136
N Error
1 25.00
ø (MHz)
13.00
N Error
1 8.99
14.2848
N Error
1 0.00
16.00
N Error
1 12.01
18.00
N Error
2 15.99
Table 14-7 Maximum Bit Rates for Various Frequencies (Smart Card Interface)
ø (MHz) Maximum Bit Rate (bits/s) N
n
7.1424 9600
0
0
10
13441
0
0
10.7136 14400
0
0
13
17473
0
0
14.2848 19200
0
0
16
21505
0
0
18
24194
0
0
The bit rate error is calculated from the following equation.
ø
Error (%) = _{1488 × 22n – 1 × B × (N + 1)} × 10⁶ –1 × 100
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