HD6433044 Datasheet, PDF (188/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

ø
Address
bus
CS ₃
RD
High
HWR
LWR
RFSH
Software standby mode
Oscillator
settling time
High-impedance
High-impedance
High-impedance
High-impedance
Figure 7-16 Signal Output Timing in Self-Refresh Mode (PSRAME = 1, DRAME = 0)
Operation in Power-Down State: The refresh controller operates in sleep mode. It does not
operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR,
RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby
mode.
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