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HD6433044 Datasheet, PDF (405/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer | |||
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Table 10-11 (d) ITU Operating Modes (Channel 3)
Register Settings
TSNC
TMDR
TFCR
TOCR TOER
TIOR3
TCR3
Operating Mode
Comple- Reset-
Output
Synchro-
mentary Synchro-
Level Master
nization MDF FDIR PWM
PWM
nized PWM Buffering XTGD Select Enable
IOA
Clear
Clock
IOB
Select
Select
Synchronous preset SYNC3 = 1 â
â
*3
ââ
*1
PWM mode
â
â PWM3 = 1 CMD1 = 0 CMD1 = 0
ââ
â
*2
Output compare A
â
â PWM3 = 0 CMD1 = 0 CMD1 = 0
ââ
IOA2 = 0
Other bits
unrestricted
Output compare B
â
â
CMD1 = 0 CMD1 = 0
ââ
IOB2 = 0
Other bits
unrestricted
Input capture A
â
â PWM3 = 0 CMD1 = 0 CMD1 = 0
ââ
EA3 ignored IOA2 = 1
Other bits Other bits
unrestricted unrestricted
Input capture B
â
â PWM3 = 0 CMD1 = 0 CMD1 = 0
ââ
EB3 ignored
Other bits
unrestricted
IOA2 = 1
Other bits
unrestricted
Counter By compare
clearing match/input
capture A
â
â
Illegal setting: *4
CMD1 = 1
CMD0 = 0
ââ
*1
CCLR1 = 0
CCLR0 = 1
By compare
match/input
capture B
â
â
CMD1 = 0 CMD1 = 0
ââ
*1
CCLR1 = 1
CCLR0 = 0
Syn-
SYNC3 = 1 â
â
chronous
clear
Illegal setting:
CMD1 = 1
CMD0 = 0
ââ
*1
CCLR1 = 1
CCLR0 = 1
Complementary
*3
â
ââ
CMD1 = 1 CMD1 = 1
*6
PWM mode
CMD0 = 0 CMD0 = 0
â
â
CCLR1 = 0 *5
CCLR0 = 0
Reset-synchronized
PWM mode
â
ââ
CMD1 = 1 CMD1 = 1
*6
CMD0 = 1 CMD0 = 1
â
â
CCLR1 = 0
CCLR0 = 1
Buffering
(BRA)
â
â
BFA3 = 1 â â
*1
Other bits
unrestricted
Buffering
(BRB)
â
â
BFB3 = 1 â â
*1
Other bits
unrestricted
Legend: Setting available (valid). â Setting does not affect this mode.
Notes: 1. Master enable bit settings are valid only during waveform output.
2. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
3. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.
4. The counter cannot be cleared by input capture A when reset-synchronized PWM mode is selected.
5. In complementary PWM mode, select the same clock source for channels 3 and 4.
6. Use the input capture A function in channel 1.
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