HD6433044 Datasheet, PDF (523/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

TEND flag is set to 1, a transmit-data-empty interrupt (TXI) is requested. If the RIE bit is set to 1
to enable interrupt requests, when a transmit error occurs and the ERS flag is set to 1, a
transmit/receive-error interrupt (ERI) is requested.
The timing of TEND flag setting depends on the GM bit in SMR. The timing is shown in figure
14-6.
If the TXI interrupt activates the DMAC, the number of bytes designated in the DMAC can be
transmitted automatically, including automatic retransmit.
For details, see Interrupt Operations and Data Transfer by DMAC in this section.
Start
Initialize
Start transmitting
No
FER/ERS = 0 ?
Yes
No
TEND = 1 ?
Yes
Write data in TDR and clear
TDRE flag to 0 in SSR
Error handling
No
All data
transmitted ?
Yes
No
FER/ERS = 0 ?
Yes
No
TEND = 1 ?
Yes
Clear TE bit to 0
Error handling
End
Figure 14-4 Transmit Flowchart (Example)
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