HD6433044 Datasheet, PDF (589/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

18.5.4 RAM Control Register (RAMCR)
The RAM control register (RAMCR) enables flash-memory updates to be emulated in RAM, and
indicates flash memory errors.
Bit
7
6
5
4
3
2
1
0
FLER —
—
— RAMS RAM2 RAM1 RAM0
Initial value
0
1
1
1
0
0
0
0
R/W
R
—
—
—
R/W R/W R/W R/W
Bit 7—Flash Memory Error (FLER): Indicates that an error occurred while flash memory was
being programmed or erased. When bit 7 is set, flash memory is placed in an error-protect
mode.*¹
Bit 7
FLER
Description
0
Flash memory is not write/erase-protected
(is not in error protect mode*¹)
(Initial value)
[Clearing conditions]
Reset or hardware standby mode
1
Indicates that an error occurred while flash memory was being programmed or
erased, and error protection*¹ is in effect
[Setting conditions]
Flash memory was read*² while being programmed or erased (including vector or
instruction fetch, but not including reading of a RAM area overlapped onto flash
memory).
A hardware exception-handling sequence (other than a reset, trace exception,
invalid instruction, trap instruction, or zero-divide exception) was executed just
before programming or erasing.
The SLEEP instruction (for transition to sleep mode or software standby mode) was
executed during programming or erasing.
A bus was released during programming or erasing.
Notes: 1. For details, see section 18.7.8, Protect Modes.
2. The read data has undetermined values.
580